EP4SGX180DF29I3N Datasheet, PDF (67/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–59
Table 1–45 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate equal to or higher than 1.25 Gbps.
Table 1–45. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher
than 1.25 Gbps
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
F1
10,000
25.000
F2
17,565
25.000
F3
1,493,000
0.350
F4
50,000,000
0.350
Figure 1–6 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for
a data rate less than 1.25 Gbps.
Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Less than 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
baud/1667
20 MHz
Frequency
When the data rate is equals to 800 Mbps, the LVDS soft-CDR/DPA sinusoidal jitter
tolerance allows up to 0.1 UI (125 ps) for jitter frequencies between 479.9 kHz and
20 MHz.
DLL and DQS Logic Block Specifications
Table 1–46 lists the DLL frequency range specifications for Stratix IV devices.
Table 1–46. DLL Frequency Range Specifications for Stratix IV Devices (Part 1 of 2)
Frequency
Mode
0
1
2
3
Frequency Range (MHz)
–2/–2×
Speed Grade
90-140
120-180
150-220
180-280
–3
Speed Grade
90-130
120-170
150-210
180-260
–4
Speed Grade
90-120
120-160
150-200
180-240
Available Phase Shift
22.5°, 45°, 67.5°, 90°
30°, 60°, 90°, 120°
36°, 72°, 108°, 144°
45°, 90°,135°, 180°
DQS Delay Buffer
Mode ⁽¹⁾
Low
Low
Low
Low
Number of
Delay
Chains
16
12
10
8
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum