EP4SGX180DF29I3N Datasheet, PDF (39/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–31
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 7 of 8)
Symbol/
Description
Conditions
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode ⁽¹⁴⁾
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
N  18
channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
–1 Industrial Speed
Grade
Min Typ Max
— — 400
— — 650
–2 Industrial Speed
Grade
Min Typ Max
— — 400
— — 650
–3 Industrial Speed
Grade
Min Typ Max
— — 400
— — 650
CMU PLL0 and CMU PLL1
Supported data
range
—
CMU PLL lock time
from
—
pll_powerdown
de-assertion
600 — 11300 600 — 10312.5 600 — 8500
— — 100 — — 100 — — 100
ATX PLL (6G)
Supported Data
Range
/L = 1
/L = 2
/L = 4
4800-5400 and
6000-6500
2400-2700 and
3000-3250
1200-1350 and
1500-1625
4800-5400 and
6000-6500
2400-2700 and
3000-3250
1200-1350 and
1500-1625
4800-5400 and
6000-6500
2400-2700 and
3000-3250
1200-1350 and
1500-1625
ATX PLL (10G)
Supported Data
Range
—
9900 — 11300 9900 — 10312.5
—
Transceiver-FPGA Fabric Interface
Interface speed
—
(non-PMA Direct)
Interface speed
—
(PMA Direct)
25 — 325 25 — 325 25 — 265.625
50 — 325 50 — 325 50 — 325
Unit
ps
ps
Mbps
s
Mbps
Mbps
Mbps
Mbps
MHz
MHz
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum