EP4SGX180DF29I3N Datasheet, PDF (40/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–32
Table 1–24. Transceiver Specifications for Stratix IV GT Devices (Part 8 of 8)
Symbol/
Description
–1 Industrial Speed –2 Industrial Speed –3 Industrial Speed
Conditions
Grade
Grade
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Digital reset pulse
width
—
Minimum is two parallel clock cycles
—
Notes to Table 1–24:
(1) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter Only mode. The minimum reconfig_clk
frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to the
Dynamic Reconfiguration in Stratix IV Devices chapter.
(2) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase
jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f.
(3) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) You must use the 1.2-V RXV_ICM setting if the input serial data standard is LVDS.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive
the minimum eye opening requirement with Receiver Equalization enabled.
(7) The rate matcher supports only up to ± 300 ppm.
(8) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–2 on page 1–33.
(9) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual
mode. Refer to Figure 1–2 on page 1–33.
(10) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–2 on page 1–33.
(11) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–3 on page 1–33.
(12) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the “Left/Right PLL
Requirements in Basic (PMA Direct) Mode” section in the Transceiver Clocking in Stratix IV Devices chapter.
(13) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(14) For applications that require low transmit lane-to-lane skew, use Basic (PMA Direct) xN to achieve PMA-Only bonding across all channels in the link.
You can bond all channels on one side of the device by configuring them in Basic (PMA Direct) xN mode. For more information about clocking
requirements in this mode, refer to the “Basic (PMA Direct) Mode Clocking” section in the Transceiver Clocking in Stratix IV Devices chapter.
(15) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels
physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta
time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
(16) To support data rates lower than 600-Mbps specification through oversampling, use the CDR in LTR mode only.
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum