EP4SGX180DF29I3N Datasheet, PDF (64/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–42. High-Speed I/O Specifications ^{(1), (2)} (Part 3 of 3)
Symbol
TCCS
Conditions
–2/–2× Speed Grade –3 Speed Grade
–4 Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
True Differential I/O Standards — — 100 — — 100 — — 100 ps
Emulated Differential I/o
Standards
— — 250 — — 250 — — 250 ps
Receiver
True Differential I/O
Standards -
SERDES factor J = 3 to 10 ⁽¹¹⁾ 150 — 1600 150 — 1250 150 — 1250 Mbps
f_HSDRDPA (data rate)
SERDES factor J = 3 to 10
(5)
—
(8)
(5)
—
(8)
(5)
—
(8) _Mbps
f_HSDR (data rate)
SERDES factor J = 2,
Uses DDR Registers
SERDES factor J = 1,
Uses an SDR Register
(5)
—
(6)
(5)
—
(6)
(5)
—
(6) _Mbps
(5)
—
(6)
(5)
—
(6)
(5)
—
(6) _Mbps
DPA Mode
DPA run length
—
— — 10000 — — 10000 — — 10000 UI
Soft CDR mode
Soft-CDR PPM
tolerance
—
—
—
300
—
—
300
—
—
300
±
PPM
Non DPA Mode
Sampling Window
—
— — 300 — — 300 — — 300 ps
Notes to Table 1–42:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) For 820, 530, 360, and 290 density devices, the frequency is 762 MHz.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (f_OUT) provided you can close the design timing and the
signal integrity simulation is clean.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(9) This is achieved by using the LVDS and DPA clock network.
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(11) The f_MAX specification is based on the fast clock used for serial data. The interface f_MAX also depends on the parallel clock domain, which is design
dependent and requires timing analysis.
(12) This only applies to DPA and soft-CDR modes.
(13) This only applies to LVDS source synchronous mode.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
January 2014 Altera Corporation