EP4SGX180DF29I3N Datasheet, PDF (55/82 Pages) Altera Corporation – Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–47
Transceiver Datapath PCS Latency
f For more information about:
■ Basic mode PCS latency, refer to Figure 1-90 through Figure 1-97 in the Transceiver
Architecture in Stratix IV Devices chapter.
■ PCIe mode PCS latency, refer to Figure 1-102 in the Transceiver Architecture in
Stratix IV Devices chapter.
■ XAUI mode PCS latency, refer to Figure 1-119 in the Transceiver Architecture in
Stratix IV Devices chapter.
■ GIGE mode PCS latency, refer to Figure 1-128 in the Transceiver Architecture in
Stratix IV Devices chapter.
■ SONET/SDH mode PCS latency, refer to Figure 1-136 in the Transceiver
Architecture in Stratix IV Devices chapter.
■ SDI mode PCS latency, refer to Figure 1-141 in the Transceiver Architecture in Stratix
IV Devices chapter.
■ (OIF) CEI PHY mode PCS latency, refer to Figure 1-143 in the Transceiver
Architecture in Stratix IV Devices chapter.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), TriMatrix, configuration, JTAG, and chip-wide reset (Dev_CLRn)
specifications.
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column, unless otherwise specified.
Clock Tree Specifications
Table 1–33 lists the clock tree specifications for Stratix IV devices.
Table 1–33. Clock Tree Performance for Stratix IV Devices
Symbol
Performance
Unit
–2/–2× Speed Grade –3 Speed Grade –4 Speed Grade
Global clock and
Regional clock
800
700
500
MHz
Periphery clock
550
500
500
MHz
January 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum