EPF10K100ARI240-3 Datasheet, PDF (62/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Table 35. EAB Timing Macroparameters Notes (1), (6)
Symbol
t_EABAA
t_EABRCCOMB
t_EABRCREG
t_EABWP
t_EABWCCOMB
t_EABWCREG
t_EABDD
t_EABDATACO
t_EABDATASU
t_EABDATAH
t_EABWESU
t_EABWEH
t_EABWDSU
t_EABWDH
t_EABWASU
t_EABWAH
t_EABWO
Parameter
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Conditions
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