EPF10K100ARI240-3 Datasheet, PDF (55/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics for EPF10K250A Device
50
40
Typical I_O
Output
30
Current (mA)
20
10
I_OL
V_CCINT = 3.3 V
V_CCIO = 3.3 V
Room Temperature
I_OH
1
2
3
4
V_O Output Voltage (V)
50
40
Typical I_O
Output
30
Current (mA)
20
10
I_OL
V_CCINT = 3.3 V
V_CCIO = 2.5 V
Room Temperature
I_OH
1
2
3
4
V_O Output Voltage (V)
Timing Model
The continuous, high-performance FastTrack Interconnect routing
resources ensure predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Device performance can be estimated by following the signal path from a
source, through the interconnect, to the destination. For example, the
registered performance between two LEs on the same row can be
calculated by adding the following parameters:
■ LE register clock-to-output delay (t_CO)
■ Interconnect delay (t_SAMEROW)
■ LE look-up table delay (t_LUT)
■ LE register setup time (t_SU)
The routing delay depends on the placement of the source and destination
LEs. A more complex registered path may involve multiple combinatorial
LEs between the source and destination LEs.
Altera Corporation
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