EPF10K100ARI240-3 Datasheet, PDF (124/128 Pages) Altera Corporation – Embedded Programmable Logic Device Family

FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Figure 32. I_CCACTIVE vs. Operating Frequency (Part 3 of 3)
EPF10K250A
3,500
3,000
2,500
I_CC Supply _2,000
Current (mA)
1,500
1,000
500
0
20
40
60
80
100
Frequency (MHz)
Configuration &
Operation
f
The FLEX 10K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
See Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000
Devices) for detailed descriptions of device configuration options, device
configuration pins, and for information on configuring FLEX 10K devices,
including sample schematics, timing diagrams, and configuration
parameters.
Operating Modes
The FLEX 10K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The FLEX 10K POR time does not exceed 50 µs.
During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device. The I/O pins are tri-stated during power-up, and before and
during configuration. Together, the configuration and initialization
processes are called command mode; normal device operation is called user
mode.
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