EV1380QI Datasheet, PDF (6/18 Pages) Enpirion, Inc. – 8a synchronous highly integrated dc-dc

EV1380 Datasheet
PARAMETER
V_POK Logic Low level
V_POK Logic high level
POK Current Sink
Capability
VTT Tracking VDDQ
Enable Pin Current
Logic Low Threshold
Logic High Threshold
S_OUT Low Level
S_OUT High Level
M/S Pin Logic Low
Threshold
M/S Pin Logic High
Threshold
SYMBOL
TEST CONDITIONS
With 4mA current sink into P_OK pin
MIN
3.07V ≤ AVIN ≤ 3.53V
VDDQ – 2*VTT
VDDQ > 1V, VDDQ Rate of change
at 1V/ms
-25
I_EN
Tied to VDDQ through a 10k
V_B-LOW
ENABLE, S_IN, VDDQOK
V_B-HIGH
ENABLE, S_IN, VDDQOK
1.8
V_{S_OUT_LOW}
V_{S_OUT_HIGH}
2.0
V_T-LOW
Threshold voltage for Logic Low
Threshold voltage for Logic High
V_T-HIGH (internally pulled high; can be left
2.0
floating to achieve logic high)
TYP
0.7
AVIN
4
MAX
1
UNITS
V
V
mA
+25
mV
50
A
0.4
V
V
0.4
V
V
0.4
V
2.7
V
The ternary pin has 100k to
AGND and another 100k to an
See
M/S Pin Input Current
I_ITERN
internal 2.5V supply. If connecting
Figure
A
to AVIN recommend using a series
7.
resistor. See Figure 7.
With 2 converters in parallel, the
Current Balance
I_OUT
difference between any two parts.
+/-10
%
AVIN<50mV, R_TRACE< 2 m
Note 1: Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
08888
6
March 18, 2015
www.altera.com/enpirion
Rev C