EV1380QI Datasheet, PDF (11/18 Pages) Enpirion, Inc. – 8a synchronous highly integrated dc-dc

signal is asserted high when rising VOUT
voltage crosses 46% (nominal) of VDDQ. POK
is de-asserted low ~64 clock cycles after the
falling VOUT voltage crosses 45% (nominal) of
VDDQ. POK is also de-asserted if VOUT
exceeds 55% (nominal) of VDDQ. For proper
POK thresholds, the input voltage divider must
generate VREF = ~0.4*VDDQ.
Over Current Protection
The current limit function is achieved by
sensing the current flowing in the hi-Side FET.
The OCP trip point is nominally set to 225% of
maximum rated load at VDDQ=1.5V. When the
sensed current exceeds the current limit, both
power FETs are turned off for the rest of the
switching cycle. If the over-current condition
lasts only a few switching cycles, normal PWM
operation is resumed. If the over-current
condition persists, the circuit will continue to
protect the load by entering a hiccup mode. In
the hiccup mode, the output is disabled for
approximately 20ms and then it goes through a
soft-start. The output will no longer track the
input voltage briefly as a result of the fault
EV1380 Datasheet
condition. This cycle can continue indefinitely
as long as the over current condition persists.
Thermal Overload Protection
Temperature sensing circuits in the controller
will disable operation when the Junction
temperature exceeds approximately 150ºC.
When the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start cycle.
Input Under-Voltage Lock-Out
When the controller voltage AVIN is below a
required voltage level (V_UVLOR) for normal
operation, converter switching is inhibited. The
lock-out threshold has hysteresis to prevent
chatter. When the device is operating normally,
the input voltage must fall below the lower
threshold (V_UVLOF) for the device to stop
switching.
Application Information / Layout Recommendation
Soft-start Capacitor Selection
requirement ensures proper POK operation.
A soft-start capacitor is recommended on the
EV1380QI’s VREF pin. The soft start capacitor
serves as both a noise filter for noise on VDDQ
as well as a slew rate limiter for fast VDDQ
input ramps. The soft start time constant is
determined by the value of this capacitor and
the input divider resistors R_C and R_D. See
figure 5. For most applications, Altera
recommends a 0.1µF capacitor on this node.
Output Voltage Programming and loop
Compensation
V_CNTRL
V_DDQ
C_IN
R_C
R_D
SCHOTTKY
SW
VDDQ
VOUT
EV1380QI
ENABLE
AVIN
VFB
PGND
PGND
VREF
CSS
AGND FQADJ
C_AVIN
R_FS
V_TT
R₁
R_A ^RPD _COUT
C_A
R_B
The output voltage of EV1380QIQI is
determined by the two voltage dividers as
shown in the simplified application diagram of
Figure 5.
The VDDQ voltage divider consisting of R_C and
R_D should be selected to make VREF = ~0.4 *
VDDQ for proper POK operation. Altera
recommends R_C = 3.01k and R_D = 2k. This
Figure 5: Typical Application Schematic
In steady state, VREF = VFB, and VOUT = 0.5
*VDDQ with proper selection of R_A and R_B.
R_A and R_B are calculated using the equations
in Figure 6. For best voltage accuracy 0.1%
resistors are recommended for R_AR_D. For
example, for VDDQ = 1.5V, R_A = 60.4k,
08888
11
March 18, 2015
www.altera.com/enpirion
Rev C