EV1380QI Datasheet, PDF (10/18 Pages) Enpirion, Inc. – 8a synchronous highly integrated dc-dc

and output dividers, the output voltage of the
EV1380QI will produce an Output Voltage
which tracks to ½ VDDQ. The EV1380QI can
continuously source or sink currents up to 8A.
The 1.5MHz nominal switching frequency
enables small-size input and output capacitors.
Soft-Start and Soft-Shutdown
The EV1380QI is expected to operate with the
controller power supply (AVIN) ON, VDDQ
ramped up and down at a relatively slow rate
(~1V/mS), and ENABLE tied to VDDQ through
a 10k resistor. It is also acceptable for VDDQ
to be dynamically scaled within a small voltage
range. If, however, VDDQ should ramp up at a
high rate, a capacitor connected between
VREF and AGND provides the soft-start
function to limit in-rush current. The soft-start
time constant is determined by the input
voltage divider and the soft-start capacitor.
See figure 5.
Pre-Bias Start-up
The EV1380QI supports start up into a pre-
biased load. Allowable pre-bias is in the range
of 0% to 40% of the programmed output
voltage. The Pre-Bias feature is controlled by
the EN_PB pin. For the pre-Bias feature to
function properly, VDDQ must be stable;
Enable must be toggled; and a pre-bias must
be present at the output.
Phase-Lock Operation:
With M_S pin floating or at a logical ‘0,’ the
internal switching clock of the DC/DC converter
can be phase-locked to a clock signal applied
to S_IN. When a clock signal is present at
S_IN, an activity detector recognizes the
presence of the clock signal and the internal
oscillator phase locks to the external clock. The
external clock could be the system clock or the
output of another EV1380QI. A delayed version
of the phase locked clock is output at S_OUT.
The clock frequency should be within 1.25MHz
to 1.75MHz for guaranteed phase-lock. Two
EV1380QI devices on a system board may be
daisy chained with appropriate phase delays to
reduce or eliminate input ripple as well as
avoid beat frequency components.
EV1380 Datasheet
Master / Slave (Parallel) Operation:
Up to two EV1380QI devices may be
connected in a Master / Slave configuration to
handle larger load currents. The Master
device’s switching clock may be phase-locked
to an external clock source or another
EV1380QI. The device is placed in Master
mode by pulling the M_S pin low or in Slave
mode by pulling M_S pin high. When this pin is
in Float state, parallel operation is not possible.
In Master mode, the internal PWM signal is
output on the S_OUT pin. The PWM signal at
S_OUT is delayed relative to the Master
device’s internal PWM signal. This PWM
signal from the Master is fed to the Slave
device at its S_IN input. The Slave device acts
like an extension of the power FETs in the
Master. The inductor in the slave prevents
crow-bar currents from Master to slave due to
timing delays. Altera does not recommend
paralleling more than 2 EV1380QI’s.
POK Operation
The internal POK signal is asserted when
VDDQ > 0.3V and 0.45*VDDQ < VOUT <
0.55*VDDQ, indicating VOUT is tracking
VDDQ. This assertion range assumes typical
VDDQ slew rates associated with VDDQ POL
regulators. For typical VDDQ POL regulators,
the VDDQ ramp rate will range from 0.5
V/mSec to 2 V/mSec. Within this range of slew
rates, the speed of the POK circuit, the loop
bandwidth, and the delay caused by the soft-
start capacitor on the VREF pin will not
significantly affect the measured POK
threshold. For much faster VDDQ ramp rates,
hot-plug slew rates for example, the speed and
latency of the elements will cause the
measured VOUT voltage where POK is valid to
be higher than the actual threshold.
The internal EV1380QI POK is AND’ed with
the VDDQOK input. The VDDQOK input is
driven by the upstream VDDQ regulator’s POK
output. Normally the VDDQOK input indicates
that VDDQ has settled to the required level. If
VDDQ is dynamically switched, VDDQOK is
expected to mask the EV1380QI POK during
the voltage transition. POK is not guaranteed
to be valid when VDDQ < 300mV. The POK
08888
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March 18, 2015
www.altera.com/enpirion
Rev C