EV1380QI Datasheet, PDF (3/18 Pages) Enpirion, Inc. – 8a synchronous highly integrated dc-dc

EV1380 Datasheet
PIN
49
50
51
53
54
55
56
57
58
59
60
61
62-63
69
NAME
S_OUT
M/S
ENABLE
AGND
POK
VFB
EAOUT
VREF
VSENSE
EN_PB
FQADJ
VDDQOK
NC(SW)
PGND
FUNCTION
Digital Output. Depending on the M/S pin, either a clock signal synchronous with the
internal switching frequency or the PWM signal is output on this pin. Leave this pin
floating if it is not used.
This is a Ternary Input put. Floating the pin disables parallel operation. A low level
configures the device as Master and a High level configures the device as a slave.
This is the Device Enable pin. Tie this pin to VDDQ with a 10k resistor.
This is the quiet ground for the control circuits. Connect to the ground plane with a via.
POK is a logical AND of VDDQOK and the internally generated POK of the EV1380QI.
POK is an open drain logic output that requires an external pull-up resistor. POK is
logic high when VOUT is within -10% to +10% of VOUT nominal. This pin guarantees
a logic low even when the EV1380QI is completely un-powered. This pin can sink a
maximum 4mA. The pull-up resistor may be connected to a power supply other than
AVIN or VDDQ but the voltage should be <3.6Volts.
This is the External Feedback input pin. A resistor divider connects from the output to
AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward
capacitor is required across the upper resistor.) The output voltage regulates so as to
make the VFB node voltage = VREF.
Optional Error Amplifier output. Allows for customization of the control loop.
External voltage reference input. A resistor divider connects from VDDQ to AGND. The
mid-point of the resistor divider is connected to VREF. The resistor divider has to be
chosen to make the voltage applied to this pin ~0.4*VDDQ. An optional capacitor (for
soft start) may be connected from VREF to AGND.
Connect this pin to VOUT.
This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support
start-up under a pre-biased load. This pin is pulled high internally.
Tie this pin to AGND through a 13k resistor.
This is an active high input pin that indicates the externally supplied VDDQ has
reached its POK level. This pin should be tied to the VDDQ regulator POK output, or let
float if unused.
NO CONNECT: These pins are internally connected to the common switching node of
the internal MOSFETs. They must be soldered to PCB but not be electrically connected
to any external signal, ground, or voltage. Failure to follow this guideline may result in
device damage.
Device thermal pad to be connected to the system GND plane for heatsinking
purposes. See Layout Recommendations section.
08888
3
March 18, 2015
www.altera.com/enpirion
Rev C