EP4SE230F29I4N Datasheet, PDF (57/82 Pages) Altera Corporation – Stratix IV Device Handbook

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–49
Table 1–34. PLL Specifications for Stratix IV Devices (Part 2 of 2)
Symbol
Parameter
Min Typ
Max
Unit
t_{OUTCCJ_DC} ⁽⁶⁾
Cycle to Cycle Jitter for dedicated clock output
(F_OUT ≥ 100 MHz)
Cycle to Cycle Jitter for dedicated clock output
(F_OUT < 100 MHz)
—
—
—
—
t_{OUTPJ_IO} ⁽⁶⁾,
(9)
Period Jitter for clock output on regular I/O
(F_OUT ≥ 100 MHz)
Period Jitter for clock output on regular I/O
(F_OUT < 100 MHz)
—
—
—
—
t_{OUTCCJ_IO} ⁽⁶⁾,
(9)
Cycle to Cycle Jitter for clock output on regular I/O
(F_OUT ≥ 100 MHz)
Cycle to Cycle Jitter for clock output on regular I/O
(F_OUT < 100 MHz)
—
—
—
—
Period Jitter for dedicated clock output in cascaded PLLs
t_{CASC_OUTPJ_DC} ^(FOUT ^{≥100MHz)}
—
—
(6)_, (7)
Period Jitter for dedicated clock output in cascaded PLLs
(F_OUT < 100MHz)
—
—
f_DRIFT
Frequency drift after PFDENA is disabled for duration of
100 us
—
—
175
ps (p-p)
17.5
mUI (p-p)
600
ps (p-p)
60
mUI (p-p)
600
ps (p-p)
60
mUI (p-p)
250
ps (p-p)
25
mUI (p-p)
±10
%
Notes to Table 1–34:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f_VCO specification.
(3) This specification is limited by the lower of the two: I/O F_MAX or F_OUT of the PLL.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 120 ps.
(5) F_REF is fIN/N when N = 1.
(6) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 1–51 on page 1–62.
(7) The cascaded PLL specification is only applicable with the following condition:
A. Upstream PLL: 0.59Mhz  Upstream PLL BW < 1 MHz
B. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–49 on
page 1–61.
March 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum