EP4SE230F29I4N Datasheet, PDF (52/82 Pages) Altera Corporation – Stratix IV Device Handbook

1–44
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–30. Transceiver Block Jitter Specifications for Stratix IV GX Devices ⁽¹⁾, ⁽²⁾ (Part 9 of 9)
Symbol/
Description
Conditions
–3 Commercial/ –3 Military ⁽³⁾ and
–2 Commercial
Industrial
–4 Commercial/
Speed Grade
and –2× Commercial
Speed Grade
Industrial Speed
Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Sinusoidal Jitter
tolerance at 3072 Mbps
Jitter Frequency = 21.8
KHz
Pattern = CJPAT
Jitter Frequency =
1843.2 MHz to 20 MHz
Pattern = CJPAT
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
UI
> 0.1
UI
Notes to Table 1–30:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The Jitter numbers are valid for the stated conditions only.
(3) Stratix IV GX devices in military speed grade only support selected transceiver configuration up to 3125 Mbps. For more information, contact
Altera sales representative.
(4) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(5) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(6) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(7) The jitter numbers for PCI Express (PIPE) (PCIe) are compliant to the PCIe Base Specification 2.0.
(8) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(9) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(10) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(11) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The fibre channel transmitter jitter generation numbers are compliant to the specification at _T interoperability point.
(14) The fibre channel receiver jitter tolerance numbers are compliant to the specification at _R interoperability point.
(15) You must use the ATX PLL adjacent to the transceiver channels to meet the transmitter jitter generation compliance in PCIe Gen2 ×8 modes.
(16) Stratix IV PCIe receivers are compliant to this specification provided the V_{TX-CM-DC-ACTIVEIDLE-DELTA} of the upstream transmitter is less than 50mV.
(17) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(18) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(19) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
March 2014 Altera Corporation