EP4SE230F29I4N Datasheet, PDF (24/82 Pages) Altera Corporation – Stratix IV Device Handbook

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–16
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 1–23 lists the Stratix IV GX transceiver specifications.
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 1 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade ⁽¹⁾
–3 Military ⁽²⁾
and –4
Commercial/Industrial
Speed Grade
Unit
Min Typ Max Min Typ Max Min Typ Max
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK input
pins
Phase frequency
detector (CMU PLL
and receiver CDR)
Absolute V_MAX for a
REFCLK pin
Operational V_MAX for
a REFCLK pin
Absolute V_MIN for a
REFCLK pin
Rise/fall time ⁽²¹⁾
Duty cycle
Peak-to-peak
differential input
voltage
Spread-spectrum
modulating clock
frequency
Spread-spectrum
downspread
On-chip termination
resistors
V_ICM (AC coupled)
V_ICM (DC coupled)
1.2 V PCML, 1.4 V PCML 1.5 V PCML, 2.5 V PCML, Differential LVPECL ⁽⁴⁾, LVDS, HCSL
—
50 — 697 50 — 697 50 — 637.5 MHz
—
50 — 425 50 — 325 50 — 325 MHz
—
— — 1.6 — — 1.6 — — 1.6
V
—
— — 1.5 — — 1.5 — — 1.5
V
—
-0.4 — — -0.4 — — -0.4 — —
V
—
— — 0.2 —
— 0.2 — — 0.2
UI
—
45 — 55 45 — 55 45 —
55
%
—
200 — 1600 200 — 1600 200 — 1600 mV
PCIe
30 — 33 30 — 33 30 — 33 kHz
0 to
0 to
0 to
PCIe
—
——
——
—
—
-0.5%
-0.5%
-0.5%
—
— 100 — — 100 — — 100 —

—
1100 ± 10%
1100 ± 10%
1100 ± 10%
mV
HCSL I/O
standard for
PCIe reference
250
—
550 250
—
550 250
—
550
mV
clock
March 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum