|
EP4SE230F29I4N Datasheet, PDF (34/82 Pages) Altera Corporation – Stratix IV Device Handbook | |||
|
◁ |
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1â26
Table 1â24. Transceiver Specifications for Stratix IV GT Devices (Part 2 of 8)
Symbol/
Description
Conditions
Rise/fall time
Duty cycle
Peak-to-peak
differential input
voltage
On-chip termination
resistors
VICM
Transmitter REFCLK
Phase Noise
Transmitter REFCLK
Phase Jitter (rms)
for 100 MHz
REFCLK (2)
RREF
â
â
â
â
â
10 Hz
100 Hz
1 KHz
10 KHz
100 KHz
ï³ 1 MHz
10 KHz to
20 MHz
â
â1 Industrial Speed
Grade
Min Typ Max
â â 0.2
45 â 55
â2 Industrial Speed
Grade
Min Typ Max
â â 0.2
45 â 55
â3 Industrial Speed
Grade
Min Typ Max
â â 0.2
45 â
55
200 â 1200 200 â 1200 200 â 1200
â 100 â
1200 ± 10%
â â -50
â â -80
â â -110
â â -120
â â -120
â â -130
â 100 â
1200 ± 10%
â â -50
â â -80
â â -110
â â -120
â â -120
â â -130
â 100 â
1200 ± 10%
â â -50
â â -80
â â -110
â â -120
â â -120
â â -130
â â 3 ââ
3
ââ
3
â
â
2000
± 1%
â
2000
± 1%
â
â
2000
± 1%
â
Transceiver Clocks
Calibration block
clock frequency
â
10 â 125 10 â 125 10 â 125
Dynamic
2.5/
2.5/
2.5/
reconfig_clk
clock frequency
reconfiguration 37.5 â
clock frequency (1)
â 37.5 â
(1)
50 37.5 â
(1)
50
fixedclk clock
frequency
PCIe Receiver
Detect
â 125 â
â 125
â
â 125 â
Delta time between
reconfig_clks
â
(15)
â â 2 ââ
2
ââ
2
Transceiver block
minimum
(gxb_powerdown)
â
power-down pulse
width
â 1 â â1
â
â1
â
Receiver
Supported I/O
Standards
Data rate (Single
width,
â
non-PMA Direct) (16)
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
600 â 3750 600 â 3750 600 â 3750
Unit
UI
%
mV
ï
mV
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
ï
MHz
MHz
MHz
ms
µs
Mbps
March 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
|
▷ |