EP4SE230F29I4N Datasheet, PDF (56/82 Pages) Altera Corporation – Stratix IV Device Handbook

1–48
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
PLL Specifications
Table 1–34 lists the Stratix IV PLL specifications when operating in the commercial
(0° to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction
temperature ranges.
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)
Symbol
Parameter
Min Typ
Input clock frequency (–2/–2x speed grade)
5
—
f_IN
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
5
—
5
—
f_INPFD
Input frequency to the PFD
PLL VCO operating range (–2 speed grade)
5
—
600 —
f_VCO ⁽²⁾
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
600 —
600 —
t_EINDUTY
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–2/–2x speed grade)
40
—
—
—
f_OUT
Output frequency for internal global or regional clock
(–3 speed grade)
—
—
Output frequency for internal global or regional clock
(–4 speed grade)
—
—
Output frequency for external clock output (–2 speed grade) —
—
f_{OUT_EXT}
Output frequency for external clock output (–3 speed grade) —
—
Output frequency for external clock output (–4 speed grade) —
—
t_OUTDUTY
t_FCOMP
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
45
50
—
—
t_CONFIGPLL
Time required to reconfigure scan chain
— 3.5
t_CONFIGPHASE Time required to reconfigure phase shift
—
1
f_SCANCLK
t_LOCK
scanclk frequency
—
—
Time required to lock from end-of-device configuration or
de-assertion of areset
—
—
t_DLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
PLL closed-loop low bandwidth
— 0.3
f_CLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth ⁽⁸⁾
— 1.5
—
4
t_{PLL_PSERR}
Accuracy of PLL phase shift
—
—
t_ARESET
Minimum pulse width on the areset signal
10
—
t_INCCJ ⁽⁴⁾, ⁽⁵⁾
Input clock cycle to cycle jitter (F_REF ≥ 100 MHz)
Input clock cycle to cycle jitter (F_REF < 100 MHz)
—
—
—
—
t_{OUTPJ_DC} ⁽⁶⁾
Period Jitter for dedicated clock output (F_OUT ≥ 100 MHz)
Period Jitter for dedicated clock output (F_OUT < 100 MHz)
—
—
—
—
Max
800 ⁽¹⁾
717 ⁽¹⁾
717 ⁽¹⁾
325
1600
1300
1300
60
800 ⁽³⁾
717 ⁽³⁾
717 ⁽³⁾
800 ⁽³⁾
717 ⁽³⁾
717 ⁽³⁾
55
10
—
—
100
1
1
—
—
—
±50
—
0.15
±750
175
17.5
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
scanclk
cycles
scanclk
cycles
MHz
ms
ms
MHz
MHz
MHz
ps
ns
UI (p-p)
ps (p-p)
ps (p-p)
mUI (p-p)
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
March 2014 Altera Corporation