EP4SE230F29I4N Datasheet, PDF (23/82 Pages) Altera Corporation – Stratix IV Device Handbook

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
1–15
Table 1–22. Differential I/O Standard Specifications ⁽¹⁾, ⁽²⁾ (Part 2 of 2)
I/O
Standard
BLVDS ⁽⁸⁾
V_CCIO (V) ⁽³⁾
V_ID (mV)
V_ICM(DC) (V)
Min Typ Max Min Condition Max Min Condition Max
2.375 2.5 2.625 100 —
——
—
—
V_OD (V) ⁽⁴⁾
Min Typ Max
— ——
V_OCM (V) ⁽⁴⁾
Min Typ Max
———
Notes to Table 1–22:
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 1–16.
(3) Differential clock inputs in column I/O are powered by V_{CC_CLKIN} which requires 2.5 V. Differential inputs that are not on clock pins in column I/O are
powered by V_CCPD which requires 2.5 V. All differential inputs in row I/O banks are powered by V_CCPD which requires 2.5V.
(4) RL range: 90  RL  110  .
(5) The receiver voltage input range for the data rate when D_MAX > 700 Mbps is 1.0 V  V_IN  1.6 V.
The receiver voltage input range for the data rate when D_MAX  700 Mbps is zero V  V_IN  1.85 V.
(6) The receiver voltage input range for the data rate when D_MAX > 700 Mbps is 0.85 V  V_IN  1.75 V.
The receiver voltage input range for the data rate when D_MAX  700 Mbps is 0.45 V  V_IN  1.95 V.
(7) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins.
(8) For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interfaces in Supported Altera Device
Families.
Power Consumption
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus^® II PowerPlay Power Analyzer feature.
1 You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix IV core and periphery
blocks for commercial, industrial, and military grade devices.
The final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon process,
voltage, and junction temperature conditions. There are no designations on finalized
tables.
March 2014 Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum