DE2-115 Datasheet, PDF (57/116 Pages) Altera Corporation – The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS.

Figure 4-26 Y-Cable use for both Keyboard and Mouse
Signal Name
PS2_CLK
PS2_DAT
PS2_CLK2
PS2_DAT2
FPGA Pin No.
PIN_G6
PIN_H5
PIN_G5
PIN_F5
Table 4-19 PS/2 Pin Assignments
Description
PS/2 Clock
PS/2 Data
PS/2 Clock (reserved for second PS/2 device)
PS/2 Data (reserved for second PS/2 device)
4.14 Gigabit Ethernet Transceiver
I/O Standard
3.3V
3.3V
3.3V
3.3V
The DE2-115 board provides Ethernet support via two Marvell 88E1111 Ethernet PHY chips. The
88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support
GMII/MII/RGMII/TBI MAC interfaces. Table 4-20 describes the default settings for both chips.
Figure 4-27 shows the connection setup between the Gigabit Ethernet PHY (ENET0) and FPGA.
Configuration
PHYADDR[4:0]
ENA_PAUSE
ANEG[3:0]
ENA_XC
DIS_125
HWCFG[3:0]
DIS_FC
DIS_SLEEP
SEL_TWSI
INT_POL
75/50OHM
Table 4-20 Default Configuration for Gigabit Ethernet
Description
Default Value
PHY Address in MDIO/MDC Mode 10000 for Enet0;10001 for Enet1
Enable Pause
1-Default Register 4.11:10 to 11
Auto negotiation configuration 1110-Auto-neg, advertise all capabilities, prefer
for copper modes
master
Enable Crossover
0-Disable
Disable 125MHz clock
1-Disable 125CLK
Hardware Configuration Mode 1011/1111 RGMII to copper/GMII to copper
Disable fiber/copper interface 1-Disable
Energy detect
1-Disable energy detect
Interface select
0-Select MDC/MDIO interface
Interrupt polarity
1-INTn signal is active LOW
Termination resistance
0-50 ohm termination for fiber
Here only RGMII and MII modes are supported on the board (The factory default mode is RGMII).
There is one jumper for each chip for switching work modes from RGMII to MII (See Figure 4-28).
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