DE2-115 Datasheet, PDF (43/116 Pages) Altera Corporation – The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS.

Figure 4-14 LVDS interface on HSMC connector and Cyclone IV E FPGA
Table 4-9 Pin Assignments for HSMC connector
Signal Name
FPGA Pin
Description
No.
I/O Standard
HSMC_CLKIN0
PIN_AH15
Dedicated clock input
Depending
on JP6
HSMC_CLKIN_N1 PIN_J28
HSMC_CLKIN_N2 PIN_Y28
HSMC_CLKIN_P1 PIN_J27
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
Depending
on JP7
Depending
on JP7
Depending
on JP7
HSMC_CLKIN_P2 PIN_Y27
LVDS RX or CMOS I/O or differential clock input
Depending
on JP7
HSMC_CLKOUT0 PIN_AD28
Dedicated clock output
Depending
on JP7
HSMC_CLKOUT_N1 PIN_G24
Depending
LVDS TX or CMOS I/O or differential clock input/output
on JP7
HSMC_CLKOUT_N2 PIN_V24
Depending
LVDS TX or CMOS I/O or differential clock input/output
on JP7
HSMC_CLKOUT_P1 PIN_G23
Depending
LVDS TX or CMOS I/O or differential clock input/output
on JP7
HSMC_CLKOUT_P2 PIN_V23
Depending
LVDS TX or CMOS I/O or differential clock input/output
on JP7
HSMC_D[0]
HSMC_D[1]
PIN_AE26 LVDS TX or CMOS I/O
PIN_AE28 LVDS RX or CMOS I/O
Depending
on JP7
Depending
on JP7
HSMC_D[2]
PIN_AE27 LVDS TX or CMOS I/O
Depending
on JP7
HSMC_D[3]
PIN_AF27 LVDS RX or CMOS I/O
Depending
on JP7
HSMC_RX_D_N[0] PIN_F25 LVDS RX bit 0n or CMOS I/O
Depending
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