DE2-115 Datasheet, PDF (52/116 Pages) Altera Corporation – The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS.

4.10 Using VGA
The DE2-115 board includes a 15-pin D-SUB connector for VGA output. The VGA synchronization
signals are provided directly from the Cyclone IV E FPGA, and the Analog Devices ADV7123
triple 10-bit high-speed video DAC (only the higher 8-bits are used) is used to produce the analog
data signals (red, green, and blue). It could support the SXGA standard (1280*1024) with a
bandwidth of 100MHz. Figure 4-21 gives the associated schematic.
Figure 4-21 Connections between FPGA and VGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational website (for example, search for “VGA signal timing”). Figure 4-22 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time (a) in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization
(vsync) is the similar as shown in Figure 4-22, except that a vsync pulse signifies the end of one
frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing).
Table 4-14 and Table 4-15 show different resolutions and durations of time periods a, b, c, and d
for both horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer’s website, or in the DE2_115_datasheets\VIDEO-DAC folder on the
DE2-115 System CD. The pin assignments between the Cyclone IV E FPGA and the ADV7123 are
listed in Table 4-16. An example of code that drives a VGA display is described in Sections 6.2 and
6.3.
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