DE2-115 Datasheet, PDF(41/116 Page) Altera Corporation – The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS.

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DE2-115 Datasheet, PDF (41/116 Pages) Altera Corporation – The DE2-115 package contains all components needed to use the DE2-115 board in conjunction with a computer that runs the Microsoft Windows OS.

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LCD_DATA[2]

LCD_DATA[1]

LCD_DATA[0]

LCD_EN

LCD_RW

LCD_RS

LCD_ON

LCD_BLON

PIN_L2

PIN_L1

PIN_L3

PIN_L4

PIN_M1

PIN_M2

PIN_L5

PIN_L6

LCD Data[2]

3.3V

LCD Data[1]

3.3V

LCD Data[0]

3.3V

LCD Enable

3.3V

LCD Read/Write Select, 0 = Write, 1 = Read

3.3V

LCD Command/Data Select, 0 = Command, 1 = Data 3.3V

LCD Power ON/OFF

3.3V

LCD Back Light ON/OFF

3.3V

4.7 High Speed Mezzanine Card

The DE2-115 development board contains a HSMC interface to provide a mechanism for extending

the peripheral-set of a FPGA host board by means of add-on cards. This can address todayâs high

speed signaling requirement as well as low-speed device interface support. The HSMC interface

support JTAG, clock outputs and inputs, high speed LVDS and single-ended signaling. The HSMC

connector connects directly to the Cyclone IV E FPGA with 82 pins. Signals HSMC_SDA and

HSMC_SCLK share the same bus with the respected signals I2C_SDA and I2C_SCL of the

WM8731 audio ship and ADV7180 TV decoder chip. Table 4-7 shows the maximum power

consumption of the daughter card that connects to HSMC port.

Supplied Voltage

12V

3.3V

Table 4-7

Power Supply of the HSMC

Max. Current Limit

1.5A

(1).Note the current levels indicated in Table 4-7 are based on 50% resource consumption.

If the HSMC interface is utilized with design resources exceeding 50%, please notify our support

(support@terasic.com).

(2).If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to

I2C_SDA. Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio

and video chip wonât function correctly.

The voltage level of the I/O pins on the HSMC connector can be adjusted to 3.3V, 2.5V, 1.8V, or

1.5V using JP7 (The default setting is 2.5V, see Figure 4-13). Because the HSMC I/Os are

connected to Bank 5 & 6 of the FPGA and the VCCIO voltage (VCCIO5 & VCCIO6) of these

banks are controlled by the header JP7, users can use a jumper to select the input voltage of

VCCIO5 & VCCIO6 to 3.3V, 2.5V, 1.8V, and 1.5V to control the voltage level of the I/O pins.

Table 4-8 lists the jumper settings of the JP7.

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