EP2C5F256C6N Datasheet, PDF (163/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
The actual half period is then = 3000 ps – 155 ps = 2845 ps
Table 5–58. Maximum DCD for DDIO Output on Column I/O Pins with PLL in
the Clock Path Notes (1), (2)
Column I/O Pins in the Clock Path C6
C7
C8
Unit
LVCMOS
285
400
445
ps
LVTTL
305
405
460
ps
2.5-V
175
195
285
ps
1.8-V
190
205
260
ps
1.5-V
605
645
645
ps
SSTL-2 Class I
125
210
245
ps
SSTL-2 Class II
195
195
195
ps
SSTL-18 Class I
130
240
245
ps
SSTL-18 Class II
135
270
330
ps
HSTL-18 Class I
135
240
240
ps
HSTL-18 Class II
165
240
285
ps
HSTL-15 Class I
220
335
335
ps
HSTL-15 Class II
190
210
375
ps
Differential SSTL-2 Class I
125
210
245
ps
Differential SSTL-2 Class II
195
195
195
ps
Differential SSTL-18 Class I
130
240
245
ps
Differential SSTL-18 Class II
132
270
330
ps
Differential HSTL-18 Class I
135
240
240
ps
Differential HSTL-18 Class II
165
240
285
ps
Differential HSTL-15 Class I
220
335
335
ps
Differential HSTL-15 Class II
190
210
375
ps
LVDS
110
120
125
ps
Simple RSDS
125
125
275
ps
Mini-LVDS
110
120
125
ps
Notes to Table 5–58:
(1) The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
(2) Numbers are applicable for commercial, industrial, and automotive devices.
Altera Corporation
February 2008
5–73
Cyclone II Device Handbook, Volume 1