EP2C5F256C6N Datasheet, PDF (149/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
Figure 5–5. RSDS Transmitter Clock to Data Relationship
Transmitter
Clock (5.88 ns)
Channel-to-Channel
Skew (1.68 ns)
At transmitter
tx_data[11..0]
Transmitter
Valid
Data
Transmitter
Valid
Data
At receiver
rx_data[11..0]
Valid
Valid
Data
Data
Total
Skew
t_SU (2 ns)
t_H (2 ns)
Table 5–49 shows the mini-LVDS transmitter timing budget for Cyclone II
devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is
supported for Cyclone II devices using DDIO registers. Cyclone II
devices support mini-LVDS only in the commercial temperature range.
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)
Symbol Conditions
f_{H S C L K}
×10
(input
×8
clock
frequency)
×7
×4
×2
×1
–6 Speed Grade
Min Typ Max
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 155.5
10 — 311
–7 Speed Grade
Min Typ Max
10
— 155.5
10
— 155.5
10
— 155.5
10
— 155.5
10
— 155.5
10
— 311
–8 Speed Grade
Min Typ Max
10
— 155.5
10
— 155.5
10
— 155.5
10
— 155.5
10
— 155.5
10
— 311
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
February 2008
5–59
Cyclone II Device Handbook, Volume 1