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EP2C5F256C6N Datasheet, PDF (150/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
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Timing Specifications
Table 5â49. Mini-LVDS Transmitter Timing Specification (Part 2 of 2)
Symbol Conditions
Device
Ã10
operation
Ã8
in Mbps
Ã7
Ã4
Ã2
Ã1
tD U T Y
â
TCCS
â
Output
â
jitter (peak
to peak)
tR I S E
20â80%
tF A L L
80â20%
tL O C K
â6 Speed Grade
Min Typ Max
100 â 311
80 â 311
70 â 311
40 â 311
20 â 311
10 â 311
45 â 55
â â 200
â â 500
â â 500
â â 500
â â 100
â7 Speed Grade
Min Typ Max
100 â 311
80
â 311
70
â 311
40
â 311
20
â 311
10
â 311
45
â
55
â
â
200
â
â 500
â
â 500
â
â 500
â
â 100
â8 Speed Grade
Min Typ Max
100 â 311
80
â 311
70
â 311
40
â 311
20
â 311
10
â 311
45
â
55
â
â 200
â
â 500
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
â
â 500 ps
â
â 500 ps
â
â 100 μs
In order to determine the transmitter timing requirements, mini-LVDS
receiver timing requirements on the other end of the link must be taken
into consideration. The mini-LVDS receiver timing parameters are
typically defined as tSU and tH requirements. Therefore, the transmitter
timing parameter specifications are tCO (minimum) and tCO (maximum).
Refer to Figure 5â4 for the timing budget.
The AC timing requirements for mini-LVDS are shown in Figure 5â6.
Figure 5â6. mini-LVDS Transmitter AC Timing Specification
LVDSCLK[]n
LVDSCLK[]p
LVDS[]p
LVDS[]n
Notes to Figure 5â6:
(1) The data setup time, tSU, is 0.225 Ã TUI.
(2) The data hold time, tH, is 0.225 Ã TUI.
TUI
tSU (1)
tH (2)
tSU (1)
tH (2)
5â60
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
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