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EP2C5F256C6N Datasheet, PDF (148/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
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Timing Specifications
Table 5â48. RSDS Transmitter Timing Specification (Part 2 of 2)
Symbol
Conditions
â6 Speed Grade
â7 Speed Grade
â8 Speed Grade
Unit
Min Typ Max(1) Min Typ Max(1) Min Typ Max(1)
TCCS
â
â â 200
â â 200
â â 200
ps
Output
â
jitter (peak
to peak)
â â 500
â â 500
â â 500
ps
tR I S E
20â80%,
â 500 â
â 500 â
â 500 â
ps
CL O A D = 5 pF
tF A L L
80â20%,
â 500 â
â 500 â
â 500 â
ps
CL O A D = 5 pF
tL O C K
â
â
100
â
100
â â 100
μs
Note to Table 5â48:
(1) These specifications are for a three-resistor RSDS implementation. For single-resistor RSDS in Ã10 through Ã2
modes, the maximum data rate is 170 Mbps and the corresponding maximum input clock frequency is 85 MHz.
For single-resistor RSDS in Ã1 mode, the maximum data rate is 170 Mbps, and the maximum input clock frequency
is 170 MHz. For more information about the different RSDS implementations, refer to the High-Speed Differential
Interfaces in Cyclone II Devices chapter of the Cyclone II Device Handbook.
In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
tSU and tH requirements. Therefore, the transmitter timing parameter
specifications are tCO (minimum) and tCO (maximum). Refer to Figure 5â4
for the timing budget.
The AC timing requirements for RSDS are shown in Figure 5â5.
5â58
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008
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