MT47H128M16PK-25E Datasheet, PDF (93/133 Pages) Alliance Semiconductor Corporation – 2Gb: x4, x8, x16 DDR2 SDRAM

2Gb: x4, x8, x16 DDR2 SDRAM
READ
Figure 46: READ Latency
CK#
CK
Command
Address
T0
READ
Bank a,
Col n
DQS, DQS#
DQ
T1
T2
NOP
NOP
RL = 3 (AL = 0, CL = 3)
T3
T3n
T4
T4n
T5
NOP
NOP
NOP
DO
n
CK#
CK
Command
Address
DQS, DQS#
DQ
T0
T1
T2
T3
READ
NOP
NOP
Bank a,
Col n
AL = 1
CL = 3
RL = 4 (AL = 1 + CL = 3)
NOP
T4
T4n T5
T5n
NOP
NOP
DO
n
CK#
CK
Command
Address
T0
READ
Bank a,
Col n
DQS, DQS#
T1
T2
T3
T3n
T4
T4n
T5
NOP
NOP
NOP
NOP
NOP
RL = 4 (AL = 0, CL = 4)
DQ
DO
n
Transitioning Data
Don’t Care
Notes:
1. DO n = data-out from column n.
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
93
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