MT47H128M16PK-25E Datasheet, PDF (104/133 Pages) Alliance Semiconductor Corporation – 2Gb: x4, x8, x16 DDR2 SDRAM

2Gb: x4, x8, x16 DDR2 SDRAM
WRITE
±^tDQSS. ^tDQSS is specified with a relatively wide range (25% of one clock cycle). All of
the WRITE diagrams show the nominal case, and where the two extreme cases (^tDQSS
[MIN] and ^tDQSS [MAX]) might not be intuitive, they have also been included. Figure 58
(page 105) shows the nominal case and the extremes of ^tDQSS for BL = 4. Upon com-
pletion of a burst, assuming no other commands have been initiated, the DQ will re-
main High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 59 (page 106) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 60 (page 106). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 43.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-
charge disabled) might be interrupted and truncated only by another WRITE burst as
long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture
of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated
with any command except another WRITE command, as shown in Figure 61
(page 107).
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE, ^tWTR should be met, as shown in Figure 62 (page 108). The number of clock
cycles required to meet ^tWTR is either 2 or ^tWTR/^tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. ^tWR must be
met, as shown in Figure 63 (page 109). ^tWR starts at the end of the data burst, regardless
of the data mask condition.
Table 43: WRITE Using Concurrent Auto Precharge
From Command
(Bank n)
WRITE with auto precharge
To Command
(Bank m)
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE or ACTIVATE
Minimum Delay
(with Concurrent Auto Precharge)
(CL - 1) + (BL/2) + ^tWTR
(BL/2)
1
Units
t_CK
t_CK
t_CK
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
104
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