MT47H128M16PK-25E Datasheet, PDF (86/133 Pages) Alliance Semiconductor Corporation – 2Gb: x4, x8, x16 DDR2 SDRAM

2Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 3 (EMR3)
Extended Mode Register 3 (EMR3)
The extended mode register 3 (EMR3) controls functions beyond those controlled by
the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 42. The
EMR3 is programmed via the LM command and will retain the stored information until
it is programmed again or until the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time ^tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.
Figure 42: EMR3 Definition
BA21 BA1 BA0 An2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MRS 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Extended mode
register (Ex)
E15 E14
Mode Register Set
00
Mode register (MR)
0 1 Extended mode register (EMR)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)
Notes:
1. E16 (BA2) is only applicable for densities ≥1Gb, is reserved for future use, and must be
programmed to 0.
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to 0.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
86
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