MT47H128M16PK-25E Datasheet, PDF (114/133 Pages) Alliance Semiconductor Corporation – 2Gb: x4, x8, x16 DDR2 SDRAM

REFRESH
2Gb: x4, x8, x16 DDR2 SDRAM
REFRESH
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-
terval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
t_{RFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when TC exceeds}
85°C.
Figure 68: Refresh Mode
T0
CK#
CK
CKE
T1
tCK
T2
T3
tCH tCL
T4
Ta0
Ta1
Tb0
Tb1
Tb2
Command
NOP1
PRE
NOP1
NOP1
REF
NOP1
REF2
NOP1
NOP1
ACT
Address
RA
All banks
A10
RA
One bank
Bank
Bank(s)³
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC _(MIN)
tRFC2
Indicates a break in
time scale
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possi-
ble at these times. CKE must be active during clock positive transitions.
2. The second REFRESH is not required and is only shown as an example of two back-to-
back REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
PDF: 09005aef824f87b6
2Gb_DDR2.pdf – Rev. H 10/11 EN
114
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