AK5354_04 Datasheet, PDF (9/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
OPERATION OVERVIEW
„ System Clock
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (40fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC is in operation. If these clocks
are not provided, the AK5354 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed internally. If the external clocks are not present, the AK5354 should be in the power-down mode.
„ Audio Data I/F Format
Using SDTO, BCLK and LRCK pins are connected to external system. Audio data format has two kinds of mode, the data
format is MSB-first, 2’s compliment. Setting by DIF bit. The initial value is DIF = “0”.
No. DIF bit
SDTO (ADC)
LRCK
0
0
20bit MSB justified Lch: “H”, Rch: “L”
1
1
I²S Compatible Lch: “L”, Rch: “H”
Table 1. Audio Data Format
BCLK
≥ 40fs
≥ 40fs
LRCK
01 2
BCLK(64fs)
12 13 14
20 21
31 0 1 2
12 13 14
20 21
SDTO(o)
19 18
876
0
19:MSB, 0:LSB
Lch Data
19 18
876
0
Rch Data
Figure 6. Audio Data Format (No.0)
31 0 1
19
LRCK
0 1 2 3 19 20 21 22 23 24 25
BCLK(64fs)
0 1 2 18 19 20 21 22 23 24 25
SDTO(o)
19 18
10
19 18
19:MSB, 0:LSB
Lch Data
Figure 7. Audio Data Format (No.1)
10
Rch Data
01
„ Digital High Pass Filter
The AK5354 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the
HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs). And digital HPF can be selected by ON/OFF
of HPF bit.
MS0054-E-02
-9-
2004/12