AK5354_04 Datasheet, PDF (6/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK) 256fs: Frequency
Pulse Width Low
Pulse Width High
384fs:
Frequency
Pulse Width Low
Pulse Width High
Channel Clock (LRCK) Frequency
Duty Cycle
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
2.048
28
28
3.072
23
23
8
45
11.2896
16.9344
44.1
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
312.5
130
130
-tBLKH+50
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200(Note 7)
80
80
50
50
150(Note 7)
50(Note 7)
50
Reset / Calibration Timing
PDN Pulse Width
tPW
150
PDN “↑” to SDTO
(Note 8)
tPWV
4128
max
12.8
19.2
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note: 7. fs ≥ 19.6kHz.
In the case of fs <19.6kHz, these three parameters must meet a relationship of
(tCSW + tCSS + 7 × tCCK) > 1/(32 × fs) in addition to these specifications.
For example, When tCCK=200ns and tCSS=50ns at fs=8kHz, tCSW(min) is 2457ns. When tCSW=150ns and
tCSS=50ns fs=8kHz, tCCK(min) is 530ns.
Note: 8. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0054-E-02
-6-
2004/12