AK5354_04 Datasheet, PDF (15/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
• About zero crossing operation
Comparator for zero crossing detection in the AK5354 has offset. Therefore, it is a possible that IPGA value is
changed by zero crossing timeout as zero crossing detection does not occur by a little offset of comparator.
For example, when Lch and Rch are in the state of IPGA = 30H, both channels are set to IPGA = 31H. And then
the only Lch completed zero crossing, Rch is waiting for zero crossing detection, zero crossing counter is reset
when IPGA is newly written 32H, zero crossing operation starts toward IPGA = 32H in state Lch = 31H, Rch =
30H. Internal IPGA value in the AK5354 has the registers of L/R channels independently, according to change
IPGA value independently, IPGA value of L/R channels may become a difference in level.
Therefore, if IPGA is written before zero crossing detection on zero crossing timeout, IPGA is keeping the same
value. When IPGA is finished by normal zero crossing timeout on IPGA value of L/R channels does not give a
difference in level, the change of IPGA should be written after zero crossing timeout cycle and over.
Internal zero crossing
operation completion flag
Lch Internal IPGA ^30H
Rch Internal IPGA ^30H
31H
Zero crossing
30H
32H
32H
IPGA Register ^30H
31H
32H
WR[IPGA=31H]
Reset zero crossing timer
WR[IPGA=32H]
Reset zero crossing timer
Figure 11. About Zero Crossing Operation
MS0054-E-02
- 15 -
2004/12