AK5354_04 Datasheet, PDF (13/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
Mode Control 2
Addr
02H
Register Name
Mode Control 2
RESET
D7
D6
D5
D4
D3
MONO1 MONO0 ZTM1 ZTM0
0
0
0
1
1
0
D2
D1
D0
0
DIF
0
0
0
0
MONO1-0:
Monaural Mixing
00: Stereo (RESET)
01: (L+R)/2
10: LL
11: RR
Lch ^ADC
HPF
SW1
Lch
Rch
ADC
HPF
+
x 0.5
SW2
Rch
Figure 10. Monaural mixing block
Mode
Stereo Recording
Monaural Recording
Stereo Input
Monaural Recording
Lch Input
Monaural Recording
Rch Input
SW1
Lch
(L+R)/2
SW2
Rch
(L+R)/2
MONO1
0
0
Lch
Lch
1
Rch
Rch
1
Table 2. Monaural Mode Setting
MONO0
0
1
0
1
ZTM1-0:
Setting of Zero Crossing Timeout for IPGA
00: 256/fs
01: 512/fs
10: 1024/fs
11: 2048/fs (RESET)
DIF: Select Digital Interface Format
No. DIF bit
SDTO(ADC)
LRCK
BCLK
0
0
20bit MSB justified Lch: “H”, Rch: “L” ≥ 40fs Reset
1
1
I²S Compatible Lch: “L”, Rch: “H” ≥ 40fs
Table 3. Audio Data Format
Inhibits writing at PM1 = “0”.
MS0054-E-02
- 13 -
2004/12