AK5354_04 Datasheet, PDF (12/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
„ Register Definition
Input Select
Addr
00H
Register Name
Input Select
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
HPF
RIN2 RIN1
LIN2
LIN1
0
0
0
0
0
1
0
1
HPF: Select ON/OFF of the digital HPF. (0: ON, 1: OFF)
LIN2-1: Select ON/OFF of Lch input. (0: OFF, 1: ON)
RIN2-1: Select ON/OFF of Rch input. (0: OFF, 1: ON)
Mode Control 1
Addr
01H
Register Name
Mode Control 1
RESET
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
PM1
PM0
0
0
0
0
0
0
1
1
PM1-0:
Power Management (0: Power down, 1: Power up)
PM0:Power control of IPGA
PM1:Power control of ADC
When PDN pin goes “L”, all circuit in the AK5354 can be powered-down in no relation to PM1-0. When PM1-0
goes all “0”, all circuit in the AK5354 can be also powered-down. However, the contents of control registers are
held.
In case of PM1 = “1”, MCLK is not stopped.
MS0054-E-02
- 12 -
2004/12