AK5354_04 Datasheet, PDF (14/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
[AK5354]
Input Analog PGA Control
Addr
03H
Register Name
Input Analog PGA Control
RESET
D7
ZEIP
0
D6
IPGA6
D5
IPGA5
D4
D3
D2
IPGA4 IPGA3 IPGA2
00H (MUTE)
D1
IPGA1
D0
IPGA0
ZEIP:
Select IPGA zero crossing operation (0: Disable, 1: Enable)
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing
detection or timeout independently.
In the timeout cycle, it is possible to set in ZTM1-0 bit.
When ZTM1-0 is “11”, timeout cycle is 2048/fs = 46.4ms (@fs=44.kHz).
When ZEIP is “0”, IPGA changes immediately. When PM1 is “0”, ZEIP is ignored and IPGA does
the operation which is the same as the case of ZEIP = “0”.
IPGA6-0: Input Analog PGA. 97 levels. 00H=MUTE.
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
Inhibits writing at PM0 = “0”.
DATA
60H
5FH
5EH
•
28H
27H
•
19H
18H
17H
16H
•
11H
10H
0FH
0EH
•
05H
04H
03H
02H
01H
00H
GAIN(dB)
Step
+28.0
+27.5
+27.0
•
+0.0
0.5dB
-0.5
•
-7.5
-8.0
-9.0
-10.0
•
1dB
-15.0
-16.0
-18.0
-20.0
•
2dB
-38.0
-40.0
-44.0
-48.0
4dB
-52.0
MUTE
Table 4. Input Gain Setting
Level
73
8
12
3
1
MS0054-E-02
- 14 -
2004/12