AK5354_04 Datasheet, PDF (7/19 Pages) Asahi Kasei Microsystems – Low Power 20bit ΔΣ ADC with PGA

ASAHI KASEI
„ Timing Diagram
MCLK
LRCK
BCLK
1/fCLK
tCLKH
tCLKL
1/fs
tBLK
tBLKH
tBLKL
Figure 1. Clock Timing
[AK5354]
VIH
VIL
VIH
VIL
VIH
VIL
LRCK
BCLK
SDTO
tBLR
tDLR
tDSS
D20 (MSB)
Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0)
VIH
VIL
VIH
VIL
50%VD
CSN
CCLK
CDTI
tCSS
tCCKL tCCKH
tCDS tCDH
op0
op1
op2
Figure 3. WRITE Command Input Timing
VIH
VIL
VIH
VIL
A0
VIH
VIL
MS0054-E-02
-7-
2004/12