AK4528_04 Datasheet, PDF (9/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC

ASAHI KASEI
Parameter
Symbol
min
typ
Control Interface Timing (P/S=“L”)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “L” Time
tCSW
150
CSN “↑” to CCLK “↑”
tCSS
150
CCLK “↑” to CSN “↑”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 13) tPD
150
RSTADN “↑” to SDTO valid
(Note 14) tPDV
516
PDN “↑” to SDTO valid
(Note 15) tPDV
516
Note:13. The AK4528 can be reset by bringing PDN “L”.
14. In serial mode, these cycles are the number of LRCK rising from RSTADN bit.
15. In parallel mode, these cycles are the number of LRCK rising from PDN pin.
„ Timing Diagram
1/fCLK
MCLK
tCLKH
tCLKL
1/fs
LRCK
tBCK
BICK
tBCKH
tBCKL
Clock Timing
[AK4528]
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
1/fs
VIH
VIL
VIH
VIL
VIH
VIL
MS0011-E-01
-9-
2004/01