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AK4528_04 Datasheet, PDF (14/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC | |||
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ASAHI KASEI
[AK4528]
 Parallel/Serial Mode Control
When P/S= âHâ, AK4528 is in parallel mode. The audio interface format is selected by DIF pin, and DFS and CK0-1 pins
select the frequency of MCLK.
When P/S= âLâ, AK4528 is in serial mode. The CKS1, CKS0 and DIF pins are changed to CDTI, CCLK and CSN pins
respectively. The DEM0-1 and DFS are ORed between pin and register respectively, so those are able to control by pins
even in serial mode. To control all the functions by register, set DEM0-1 and DFS pins âLâ.
 Digital High Pass Filter
The ADC has a digital high pass filter (HPF) for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at
fs=44.1kHz and also scales with sampling rate (fs). This HPF can be off for each channel by register.
 Output Volume
The AK4528 includes digital volumes (OATT) with 128 levels (including MUTE) in front of DAC. The OATT is a
pseudo-log volume linear-interpolated internally. When the level is changed, the transition to new value takes 8031 levels
(max) and is done by soft transition. Therefore, there is not any switching noise.
 De-emphasis Filter
The DAC includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter supports to three frequencies
(32kHz, 44.1kHz and 48kHz). This setting is done by contorl register and always OFF at double speed mode.
No DEM1 DEM0
Mode
0
0
0
44.1kHz
1
0
1
OFF
2
1
0
48kHz
3
1
1
32kHz
Table 6. De-emphasis control (DFS=â0â)
Default in serial
mode
MS0011-E-01
- 14 -
2004/01
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