AK4528_04 Datasheet, PDF (19/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC

ASAHI KASEI
[AK4528]
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch ATT Control
Rch ATT Control
D7
0
TE7
DIF2
SMUTE
0
0
D6
0
TE6
DIF1
0
ATTL6
ATTR6
D5
0
TE5
DIF0
0
ATTL5
ATTR5
D4
0
TE4
CMODE
0
ATTL4
ATTR4
D3
0
0
CKS1
HPFR
ATTL3
ATTR3
D2
PWVR
0
CKS0
HPFL
ATTL2
ATTR2
D1
PWAD
RSTADN
0
DEM1
ATTL1
ATTR1
D0
PWDA
RSTDAN
DFS
DEM0
ATTL0
ATTR0
Note: For address from 06H to 1FH, data should not be written.
In case of writing to 01H, write “0000” to D7-4.
PDN = “L” resets the registers to their default values.
„ Control Register Setup Sequence
The setting of clock mode or data format by control register should be done during RSTADN = RSTDAN = “0”, and
outputs of ADC/DAC should be muted.
1. In case of using PDN pin
(1) Set PDN= “H”.
(2) Set registers for clock mode, data format, etc.
(3) Cancel the reset state by setting RSTADN or RSTDAN to “1”. Refer to Reset Contorl Register (01H).
2. In case of not using PDN pin
(1) Set RSTADN = RSTDAN = “0”.
(2) Set registers for clock mode, data format, etc.
(3) Cancel the reset state by setting RSTADN or RSTDAN to “1”. Refer to Reset Contorl Register (01H).
Note: Those settings may generate pop noise. Please mute the output of ADC and DAC externally.
MS0011-E-01
- 19 -
2004/01