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AK4528_04 Datasheet, PDF (20/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC | |||
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ASAHI KASEI
[AK4528]
 Register Definitions
Addr
00H
Register Name
Power Down Control
default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
PWVR PWAD PWDA
0
0
0
0
0
1
1
1
PWDA: DAC power down
0: Power down
1: Power up
Only DAC section is powered down by â0â and then the AOUTs go Hi-Z immediately. The OATTs also go
â00Hâ. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (04H &
05H). The analog outputs should be muted externally as some pop noise may occur when entering to and
exiting from this mode.
PWAD: ADC power down
0: Power down
1: Power up
Only ADC section is powered down by â0â and then the SDTO goes âLâ immediately. The contents of all
register are not initialized and enabled to write to the registers.
After exiting the power down mode, ADC outputs â0â during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up
All sections are powered down by â0â and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go â0â and
PWVR goes â1â, only VREF section can be powered up.
Addr
01H
Register Name
Reset Control
default
D7
D6
D5
D4
D3
TE7
TE6
TE5
TE4
0
0
0
0
0
0
D2
D1
D0
0
RSTADN RSTDAN
0
0
0
TE7-4: Test Control Register Enable
Must be fixed to â0000â.
RSTDAN: DAC reset
0: Reset
1: Normal Operation
The internal timing is reset by â0â and then the AOUTs go VCOM voltage immediately. The OATTs also
go â00Hâ. But the contents of all register are not initialized and enabled to write to the registers. After
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The
analog outputs should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
RSTDAN: ADC reset
0: Reset
1: Normal Operation
The internal timing is reset by â0â and then SDTO goes âLâ immediately. But the contents of all register are
not initialized and enabled to write to the register.
After exiting the power down mode, ADCs output â0â during first 516 LRCK cycles.
MS0011-E-01
- 20 -
2004/01
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