AK4528_04 Datasheet, PDF (18/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC

ASAHI KASEI
[AK4528]
„ Serial Control Interface
The serial control interface is enabled by the P/S pin = “L”. The internal registers are written by the 3-wire µP interface
pins: CSN, CCLK, CDTI. The data on this interface consists of Chip address (2bits, fixed to C0/1 = “01”) Read/Write
(1bit, fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in
on the rising edge of CCLK. Data is latched after a low-to-high transition of CSN. The maximum clock speed of the
CCLK is 5MHz. The CSN should be “H” if no access. The chip address is fixed to “10”. Writing is invalid for the access
to the chip address except for “10”. PDN = “L” resets the registers to their default values.
Function
Parallel mode Serial mode
Double speed
O
O
De-emphasis
O
O
SMUTE
X
O
Output Digital ATT
X
O
HPF off
X
O
MCLK; 768fs@Normal Speed
384fs@Double Speed
X
O
16/20/24bit LSB justified format
X
O
Table 7. Function list (O: available, X: not available)
When PDN = “L”, internal registers are initialized. In case of changing P/S pin, please set PDN = “L” to reset the device.
In case of serial mode, the internal timings are initialized by RSTN = “0”, but the contents of registers are hold.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE only)
Register Address
Control data
Figure 9. Control I/F Timing
*AK4528 does not support the READ. C1, C0 and R/W are fixed (“101”).
MS0011-E-01
- 18 -
2004/01