AK4528_04 Datasheet, PDF (11/29 Pages) Asahi Kasei Microsystems – High Performance 24Bit 96kHz Audio CODEC

ASAHI KASEI
[AK4528]
OPERATION OVERVIEW
„ System Clock Input
The external clocks, which are required to AK4528, are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The frequency of MCLK is set by CMODE, CKS0-1 and DFS bits in serial mode, or
by CKS0-1, DFS pins in parallel mode (see Table 2 and 3). The CKS0-1 and DFS pin should be changed during the PDN
pin = “L”. The CMODE, CKS0-1 and DFS bits are changed during RSTADN = RSTDAN = “0”.
External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4528 is in normal operation mode
(PDN = “H” and at least one of ADC and DAC is in normal operation mode). If these clocks are not provided, the
AK4528 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are
not present, the AK4528 should be in the power-down mode (PDN = “L” or set both ADC and DAC power down mode
by the register).
CMODE bit CKS1 bit CKS0 bit
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
MCLK
Normal Speed
(DFS bit = “0”)
256fs
512fs
1024fs
384fs
768fs
MCLK
Double Speed
(DFS bit = “1”)
N/A
256fs
512fs
N/A
384fs
Default
Table 1. Master Clock Frequency Select in Serial Mode
CKS1 pin CKS0 pin
L
L
L
H
H
L
H
H
MCLK
Normal Speed
(DFS pin = “L”)
256fs
512fs
384fs
1024fs
MCLK
Double Speed
(DFS pin = “H”)
N/A
256fs
N/A
512fs
Table 2. Master Clock Frequency Select in Parallel Mode
MCLK
Normal Speed
(DFS = “0”)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz fs=48kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK
Double Speed
(DFS = “1”)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz fs=96kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
Table 3. Master Clock Frequencies example
Note. Do not set any mode which is not described in Table1-3.
MS0011-E-01
- 11 -
2004/01