AKD4671-B Datasheet, PDF (8/51 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in Microphone-Amplifier

[AKD4671-B]
(3) PLL Slave Mode
A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to
the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits.
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose
not matter. MCKO pin outputs the frequency selected by PS1-0 bits and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits.
(3-1) PLL Reference Clock : MCKI pin
AK4671
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
(3-1-1) Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
The jumper pins should be set as the following.
JP39
EXT
JP36
MCLK
DIR
EXT
JP33
JP38
BICK_SEL LRCK_SEL
DIR 4040 DIR 4040
JP46
4114_MCKI
JP35
PHASE
THR INV
JP7
MCKO
JP48
M/S
Master Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) to open.
<KM089000>
-8-
2007 / 05