AKD4671-B Datasheet, PDF (12/51 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in Microphone-Amplifier

[AKD4671-B]
(4) PLL Master Mode
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or
27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The
MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output
frequency is selected between 32fs or 64fs, by BCKO bit.
AK4671
MCKI
MCKO
BICK
LRCK
SDTO
SDTI
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
(4-1) Evaluation of A/D using DIT of AK4114
J12 (EXT) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
X’tal oscillator should be removed from X2.
In Master Mode, BICK and LRCK of AK4671 should be input to AK4114. Please refer to Table 2 on page 19.
The jumper pins should be set as the following.
JP39
EXT
JP48
M/S
JP36
MCLK
DIR
EXT
JP33
JP38
BICK_SEL LRCK_SEL
DIR 4040 DIR 4040
JP46
4114_MCKI
JP35
PHASE
THR INV
JP7
MCKO
Master Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
<KM089000>
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2007 / 05