AKD4671-B Datasheet, PDF (4/51 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in Microphone-Amplifier

[AKD4671-B]
(1) External Slave Mode
When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to
operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI)
should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI
is selected by FS1-0 bits.
AK4671
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 384fs, 512fs,
768fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTI
SDTO
(1-1) Evaluation of A/D using DIT of AK4114
X2 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT4 (DSP).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP33
JP38
BICK_SEL LRCK_SEL
JP35
PHASE
JP46
4114_MCKI
JP48
M/S
DIR 4040 DIR 4040 THR INV
Master Slave
(1-2) Evaluation of D/A using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP33
BICK_SEL
JP38
JP51
LRCK_SEL SDTI_SEL
JP35
PHASE
JP48
M/S
DIR 4040 DIR 4040 DIR ADC THR INV Master Slave
<KM089000>
-4-
2007 / 05