AKD4671-B Datasheet, PDF (5/51 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in Microphone-Amplifier

[AKD4671-B]
(1-3) Evaluation of Loop-back using AK4114 <default>
X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP33
BICK_SEL
JP38
JP51
LRCK_SEL SDTI_SEL
JP35
PHASE
JP46
4114_MCKI
JP48
M/S
DIR 4040 DIR 4040 DIR ADC THR INV
Master Slave
(1-4) Evaluation of Loop-back where master clock is fed externally, BICK and LRCK are generated by
on-board divider.
J12 (EXT) is used . MCLK is supplied from J12 (EXT). BICK and LRCK are generated by 74HC4040 on
AKD4671-B.
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP).
The jumper pins should be set as the following.
JP39
EXT
JP36
MCLK
DIR
EXT
JP33
JP38
JP51
BICK_SEL LRCK_SEL SDTI_SEL
JP48
M/S
DIR 4040 DIR 4040 DIR ADC Master Slave
When a termination (51Ω) is unnecessary, please set JP39 (EXT) open.
JP32 (MKFS), JP34 (BCFS), and JP37 (LRCK) should be set according to the frequency of MCLK, BICK and
LRCK.
Follows are setting examples in MCLK=256fs , BICK=64fs and LRCK=1fs.
When MCLK=384fs or 768fs, JP32, JP34, and JP37 should be set to “384” side.
.
JP32
MKFS
256fs
512fs
1024fs
384/768fs
MCKO
64fs-384
32fs-384
64fs
32fs
JP34
BCFS
JP37
LRCK
fs-384
fs
(1-5) All interface signals including master clock are fed externally
PORT4 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
The jumper pins should be set as the following.
JP36
MCLK
DIR
EXT
JP33
JP38
JP51
BICK_SEL LRCK_SEL SDTI_SEL
JP48
M/S
DIR 4040 DIR 4040 DIR ADC Maste Slave
<KM089000>
-5-
2007 / 05