AKD4671-B Datasheet, PDF (15/51 Pages) Asahi Kasei Microsystems – stereo CODEC with built-in Microphone-Amplifier

[AKD4671-B]
(1) PLLBT reference clock: SYNCA or BICKA pin
The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output
via SYNCB and BICKB pins.
AK4671
Baseband Module
SYNCA
BICKA
SDTOA
SDTIA
1fs2
≥ 16fs2
SYNC
BICK
SDTI
SDTO
Bluetooth Module
SYNCB
BICKB
1fs2
16fs2 or 32fs2
SYNC
BICK
SDTOB
SDTI
SDTIB
SDTO
(PLLBT Reference Clock: SYNCA or BICKA pin)
(1-1) SYNCA and BICKA are fed from on-board clock generator.
X1 (X’tal), PORT3 (Baseband Module) and PORT6 (Bluetooth Module) are used.
The jumper pins should be set as the following.
Please set JP42 (BCFS2) to the required frequency. Follows are setting in BICKA=32fs.
When clocks are supplied from J13 (EXT1) without using X1, JP41 (MCLK2) should be set to “EXT1”.
JP40
XTE
JP41
MCLK2
XTL
EXT1
JP42
BCFS2
256fs2
128fs2
64fs2
32fs2
16fs2
JP43
BICK2_SEL
JP45
LRCK2_SEL
JP49
PLLBT
BICKA BICKB LRCKA LRCKB
BICKA BICKB
JP62
BICKA
JP63
SYNCA
JP64
BICKB
JP65
SYNCB
JP61
SDTIB
JP60
SDTIA
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