AK4640_05 Datasheet, PDF (67/78 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4640]
3. When an external clock is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
External MCLK
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
BICK, LRCK
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
(1)
(2)
(3)
Input
40ms(max)
E xam p le :
A udio I/F Fo rm at : I²S
B IC K freq ue ncy at M a ste r M o de : 64fs
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1 ) A d d r:0 1 H , D ata:0 0 H
(2) Input external M CLK
(3 ) A d d r:0 1 H , D ata 2 0 H
(4)
(5)
Output
(4 ) A d d r:0 4 H , D ata 4 A H
(6)
Input
(5) M CK O output starts
(6 ) B IC K and L R C K inp u t start
(7)
00
XX
(7 ) A d d r:0 4 H , D ata 6 A H
Figure 49. Clock Set Up Sequence(3)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0”
(2) Input an external MCKI
(3) Power-up PLL : PMPLL bit = “0” → “1”
PLL needs 40ms lock time after the PMPLL bit = “0” → “1”.
(4) Enable MCKO output : MCKO bit = “0” → “1”
(5) MCKO is output after PLL lock time.
(6) Input BICK and LRCK that synchronized in the MCKO output.
(7) Set up MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
MS0273-E-02
- 67 -
2005/04