AK4640_05 Datasheet, PDF (41/78 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4640]
„ ALC2 Operation
Input resistance of the ALC2 (MIN pin) is 24kΩ (typ) and centered around VCOM voltage. (see Figure 31. 0dBV=1Vrms
=2.828Vpp)
The limiter detection level is proportional to HVDD. The ALC2 circuit limits the output level when the input signal
exceeds –5.2dBV (=FS−1.9dB@HVDD=3.3V). When a continuous signal of –5.2dBV or greater is input to the ALC2
circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step.
The ALC2 recovery operation uses zero crossings and gains of 1dB/step. The ALC2 recovery operation is done until the
input level of the Speaker-amp goes to –7.2dBV(=FS-3.9dB@HVDD=3.3V). The ROTM bit sets the ALC2 recovery
operation period.
When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done.
When the PMSPK bit changes from “0” to “1”, the initilization cycle (2048/fs = 46.4ms @fs=44.1kHz at ROTM bit =
“0”, 512/fs = 11.4ms @fs=44.1kHz at the ROTM bit = “1”) starts. The ALC2 is disabled during the initilization cycle and
the ALC2 starts after completing the initilization cycle.
Parameter
ALC2 Limiter operation
ALC2 Recovery operation
Operation Start Level
−5.2dBV
−7.2dBV
Period
ROTM bit = “0”
ROTM bit = “1”
2/fs = 45µs@fs=44.1kHz
2/fs = 181µs@fs=11.025kHz
2048/fs = 46.4ms@fs=44.1kHz
512/fs = 46.4ms@fs=11.025kHz
Zero-crossing Detection
Disabled
Enabled (Timeout = 2048/fs)
ATT/GAIN
0.5dB step
1dB step
Table 23. Limiter /Recovery of ALC2 at HVDD=3.3V
-3.3dBV
FS
-8dB
FS-12dB
-15.3dBV
-8dB
-3.3dBV
FS-1.9dB = -5.2dBV
3.0dBV(250mW @8ohm)
1.0dBV
0dBV
-1.9dB
+8.2dB _+8.2dB
Full-differential
+4.1dB
+2.2dB ^-3.0dBV
+2.2dB ^-5.0dBV
Single-ended
-10dBV
-11.3dBV
+8.1dB
-15.3dBV
+16.1dB
FS-3.9dB = -7.2dBV
-20dBV
-23.3dBV
-30dBV
DATT
DAC
ALC2
SPK-AMP
Figure 31. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=−8.0dB, ALC2= “1”)
MS0273-E-02
- 41 -
2005/04